(a) Fields of the Invention
The present invention relates to nitride semiconductor transistors and their fabrication methods. In particular, the present invention relates to normally-off type nitride semiconductor transistors applicable to power switching devices, and their fabrication methods.
(b) Description of Related Art
In recent years, field effect transistors (FET) made of gallium nitride (GaN)-based materials have been widely investigated for high frequency devices and high power devices. As the GaN-based nitride semiconductor, not only GaN but also aluminum nitride (AlN), indium nitride (InN), and the like are used. Since these nitride semiconductors can form various types of compound materials, they can form heterojunctions like conventional arsenic-based semiconductors such as gallium arsenide (GaAs). However, in the heterojunction of the nitride semiconductor, even though impurities are not added in the nitride semiconductors intentionally, spontaneous polarization and piezoelectric polarization produces high sheet carrier densities at the interface thereof. As a result of this, most of GaN-based heterojunction FETs exhibit depletion (normally-on) characteristics, and it is difficult to exhibit enhancement (normally-off) characteristics. Aiming at the practical applications, normally-off operation is strongly desired for FETs fabricated using the nitride semiconductor in order to make the GaN devices compatible with currently used Si-based power MOSFETs/IGBTs for safe operation.
Conventional structures of normally-off type FETs using nitride semiconductors include: a structure in which the thickness and/or the Al mole fraction of an AlGaN layer are decreased; a structure in which a gate region is partially recessed to shift a threshold voltage positively (see, for example, T. Kawasaki et al., “Solid State Devices and Materials 2005 tech. digest”, 2005, pp. 206); the structure in which a FET is fabricated on the (10-12) plane of a sapphire substrate to prevent a polarization electric field from being generated in the crystal growth direction of the nitride semiconductor (see, for example, M. Kuroda et al., “Solid State Devices and Materials 2005 tech. digest”, 2005, pp. 470); and the like.
As a promising structure for obtaining the normally-off type FET, a junction field effect transistor (JFET) is proposed in which a p-type GaN layer is formed as gate (see, for example, Japanese Unexamined Patent Publication No. 2005-244072). In a conventional JFET, a buffer layer, a channel layer of undoped GaN, and a barrier layer of n-doped AlGaN are sequentially formed over a substrate. On the barrier layer, a source electrode and a drain electrode are formed separately. Between the source electrode and the drain electrode, a gate electrode is formed with a p-GaN layer.
In the conventional JFET structure, piezoelectric polarization generated at the heterointerface between the channel layer of undoped GaN and the barrier layer of AlGaN is cancelled by piezoelectric polarization generated at the heterointerface between the barrier layer of AlGaN and the p-type GaN layer. This structure decreases the concentration of two-dimensional electron gas in an area just below the gate, whereby the normally-off characteristics can be obtained. In addition, a pn junction gate having a higher built-in potential than a Schottky junction, provides an advantage that even though a positive gate voltage is applied, a gate leakage current can be maintained at lower level.
However, unlike a silicon semiconductor, it is difficult to form p-type or n-type conductive areas selectively by ion implantation or thermal diffusion in the nitride semiconductors. Thus, a promising approach to form the p-type gate is, for example, a selective regrowth of a p-type nitride semiconductor just only at the gate area. In such selective regrowth, however, silicon which acts as a n-type impurity in nitride semiconductor is easily segregated at the regrowth interface. So it is difficult to obtain a good pn junction in this method.
Another promising approach to form the p-type gate is a selective etching method in which a p-type nitride semiconductor is deposited and etched locally remaining the portions of the p-type nitride semiconductor layer only at the gate area. This method, however, has a serious problem that the etching of the p-type nitride semiconductor layer causes electrical damages at the channel region and it is difficult to obtain good electrical properties of FETs. When the channel region is damaged by etching, the carrier concentration in the channel region between the gate and the drain decreases to cause a reduction in drain current. Moreover, trapping of electrons into defects created on the surface of the channel region or other damage-induced influences inhibit a fast switching operation, that is, a so-called current collapse occurs.